Current popular and accepted architectures primarily use synchronous circuits, these circuits are easy to verify and provided sufficient performance for early applications, this led to their rapid acceptance.
Increasingly complex and data intensive computations like machine learning are growing faster than computer scientists can find ways to scrape more performance from synchronous architectures. Synchronous architectures process unneeded computation, wasting power and time. Worst-case timing requirements of synchronous pipelines result in portions of cycles spent waiting, with no computation occurring, resulting in further wasted time. In addition, as the size and complexity of ASICs increases, the percentage of power needed to support the stable clock network required to control operation of a synchronous chip increases as well.
Asynchronous architecture is a growing field that provides solutions to these problems. The major limiting factor in research and industry adoption of this style of architecture is the availability of tools to aid researchers and developers who wish to explore the field. This summer project aims to remedy part of that problem by creating tools that will allow rapid advancement of this highly promising field.
COSC 101, COSC 102 (or equivalents) required. Basic proficiency in material taught in COSC 201 required. Strong programming skills in any language. Willingness to learn new-skills. The project will require some concepts included in various 300-level courses, it would be beneficial for students to have taken at least one 300-level computer science course. The specific tools to be created for the project can, at least in part, be adjusted based on the skills of the students selected.
Number of Student Researchers
10 weeks weeks
Applications open on 01/05/2018 and close on 02/05/2018